A non-volatile memory (NVM) cell is a semiconductor memory cell that maintains its state after power has been turned off. An example of such a cell is a stacked gate memory cell, comprising a transistor which has a source, a drain, a floating gate isolated by an oxide or other similar material, and a control gate above the floating gate.
For example, in the case of a PMOS (P-channel Metal Oxide Semiconductor) NVM cell, the current flowing through the cell depends on the voltage of the floating gate. Since the floating gate is isolated and not directly accessible for the purposes of changing its voltage, the voltage is altered via one of two mechanisms: (1) introducing some charge into the floating gate, and (2) using surrounding voltages and capacitive coupling (i.e. the capacitance between the floating gate and the surrounding elements) in order to change the floating gate voltage by applying a voltage to the control gate or other electrodes.
There are three operations that can be performed on such a stacked cell: Read, Program and Erase. Reading the stacked cell refers to applying a voltage between the source and the drain, followed by sensing the amount of current flowing between the source and drain. A high level of current flow indicates one state of the cell (e.g. the “ON” state), while a low level of current flow indicates the other state (e.g. the “OFF” state).
Programming the stacked cell refers to causing negative charges to accumulate into the floating gate. If this negative charge is large enough, the voltage will fall below a threshold voltage, and as a result the channel will be on (i.e. the channel will be conducting). When the channel is on, a Read operation will sense a high level of current flow, indicating that the stacked cell is “ON”. This in turn indicates that a “1” bit (or a “0” bit, depending on the agreed-upon convention) is stored in the cell.
Erasing the stacked cell refers to an operation which is opposite the Program operation, causing a removal of negative charges from the floating gate. As a result, the voltage of the floating gate will be positive (or simply above a voltage threshold), causing the channel to be turned off (i.e. become non-conducting). When the channel is turned off, a Read operation will sense a low level of current flow, indicating that the stacked cell is “OFF”. This in turn indicates that a “0” bit (or a “1” bit, depending on the agreed-upon convention) is stored in the cell.
Since a conventional NVM cell has only two states (one programmed state and one erased state), it can store only one bit of information. While this works well, it limits the storage capacity of the cell. Therefore, having an NVM cell capable of assuming more than two states improves memory capacity by allowing the cell to store more than one bit of information.